A self-refreshing DRAM is a dynamic random access memory which has an autonomous refresh circuit.
DRAMs are comprised of a plurality of memory storage cells in which each cell consists of a transistor and an intrinsic capacitor. The transistors are used to charge and discharge the capacitors to certain voltage levels. The capacitors then store the voltages as binary bits, 1 or 0, representative of the voltage levels. The binary 1 is referred to as a "high" and the binary 0 is referred to as a "low." The voltage value of the information stored in the capacitor of a memory cell is called the logic state of the memory cell. Due to capacitance leakage, the memory storage cells must be refreshed periodically during a refresh mode to keep the capacitors charged or discharged to ensure memory preservation. A refresh cycle normally involves cycling through the memory and performing a read/write operation in each row of the memory, in turn. A sleep mode is typically characterized as a low power mode having no active read or write operations during which data retention is desired. It is typically necessary to refresh each row of memory in the DRAM device within a time period of 4 to 256 milliseconds for data detention.
In order for refresh to occur, an external row address strobe signal* (RAS*) and an internally generated self-refresh timing signal must typically be active. When RAS* transitions to an inactive state, the refresh mode is typically exited. Automatic exiting of the refresh mode without regard to the state of the internally generated self-refresh timing signal may cause metastability of the DRAM due to glitches caused by external RAS* and the internal self-refresh timing signal opposing one another.
Thus there exists a need to prevent glitches from occurring during a termination of a self-refresh mode when a race condition exits between an external RAS* transitioning to an inactive state and an internally generated self-refresh timing signal transitioning to an active state.
There is also a need to vary the period of the refresh cycle and the period of the refresh mode to adjust the rate of refresh for changes in voltage and temperature. Changes in voltage and temperature may vary the rate of leakage of the memory storage cells requiring more or less frequent refreshing of the DRAM.